Integrated circuits (ICs) or chips contain capacitors for the purpose of storing charge, such as, for example, a dynamic random access memory (DRAM). In this case, the charge state in the capacitor represents a data bit.
A DRAM chip contains a matrix of memory cells, which are arranged in the form of rows and columns, and are addressed by word lines and bit lines. The reading of data from the memory cells or the writing of data to the memory cells is realized by activating suitable word lines and bit lines.
A DRAM memory cell usually contains a transistor connected to a capacitor. The transistor is referred to as a selection transistor and comprises, inter alia, two doping regions isolated from one another by a channel which is controlled by a gate. Depending on the direction of current flow, one doping region is referred to as the drain region and the other as the source region. The source region is connected for example to the trench capacitor, the drain region is connected to a bit line and the gate is connected to a word line. By the application of suitable voltages to the gate, the transistor is controlled in such a way that a current flow between the source region and the drain region through the channel is switched on and off.
The charge stored in the capacitor decreases over time on account of leakage currents. Before the charge has decreased to a level below a threshold value, the storage capacitor must be refreshed. For this reason, these memories are referred to as dynamic RAM (DRAM).
The central problem in known DRAM variants based on a trench capacitor is the production of a sufficiently large capacitance for the trench capacitor. This problem will be aggravated in future by the advancing miniaturization of semiconductor components. The increase in the integration density means that the area available per memory cell and thus the capacitance of the trench capacitor decrease ever further.
Sense amplifiers require a sufficient signal level for reliably reading out the information situated in the memory cell. The ratio of the storage capacitance to the bit line capacitance is crucial in determining the signal level. If the storage capacitance is too low, the ratio may be too small for generating an adequate signal.
A lower storage capacitance likewise requires a higher refresh frequency, because the quantity of charge stored in the trench capacitor is limited by its capacitance and additionally decreases due to leakage currents. If the quantity of charge falls below a minimum quantity of charge in the storage capacitor, then it is no longer possible for the information stored therein to be read out by a connected sense amplifier, the information is lost and read errors arise.
One way of avoiding read errors is to reduce the leakage currents. Leakage currents can be reduced on the one hand by transistors and on the other hand by dielectrics, such as the capacitor dielectric, for example. An undesirably reduced retention time can be lengthened by these measures.
Stacked capacitors or trench capacitors are usually used in DRAMs. In this case, a trench capacitor has a three-dimensional structure which is formed in a silicon substrate, for example. An increase in the capacitor electrode area, and thus, in the capacitance of the trench capacitor, can be achieved, for example, by etching more deeply into the substrate, and, thus by deeper trenches. In this case, the increase in the capacitance of the trench capacitor does not cause the substrate surface occupied by the memory cell to be enlarged. However, this method is also limited, since the attainable etching depth of the trench capacitor depends on the trench diameter, and, during fabrication, it is only possible to attain specific, finite aspect ratios between the trench depth and trench diameter.
As the increase in the integration density advances, the substrate surface available per memory cell decreases ever further. The associated reduction in the trench diameter leads to a reduction in the capacitance of the trench capacitor. If the capacitance of the trench capacitor is dimensioned to be so low that the charge which can be stored is insufficient for entirely satisfactory read out by the sense amplifiers connected downstream, then this results in read errors.
This problem is explained, for example, in the document DE 199 41 148, the selection transistor, which is usually arranged next to the trench capacitor, being arranged above the trench capacitor. As a result, the trench of the trench capacitor can take up a part of the substrate surface which was conventionally reserved for the transistor. Through this arrangement, the trench capacitor and the transistor share part of the substrate surface. This arrangement is made possible by an epitaxial layer grown above the trench capacitor.
What is problematic, however, is the electrical connection of the trench capacitor to the transistor. Purely lithographic methods for fabricating the electrical connection require a minimum distance between the trench capacitor and the transistor for the lithographic alignment of the individual lithographic planes with respect to one another. Through purely lithographic methods, the memory cells in the memory cell array require a relatively large area and are unsuitable for integration in a large-scale integrated cell array.
What is disadvantageous about the memory cells known from the prior art is that the resistance of the electrical connection between the trench capacitor and the source region of the transistor has a relatively large value, which slows down the access to the memory cell.
A further disadvantage of the prior art is that a sufficient retention time is only achieved by complex insulation measures which require a large number of processing steps. In this case, the electrical contact is insulated from the substrate in a complex manner.